The present invention relates to a gate driving circuit and a semiconductor device and, more particularly, to a circuit which drives the gate of a switching element and a semiconductor device.
For example, a large current and high breakdown voltage are required for a device which uses a switching element such as an IGBT (Insulated Gate Bipolar Transistor) as the output stage to drive a motor. For such an application purpose of switching, the current density of the element increases, noise at the switching time poses a problem, and the element readily breaks when a load is short-circuited. To prevent these problems, the gate output level is moderately changed at gate off.
FIG. 5 shows the arrangement of a semiconductor device including a conventional gate driving circuit. At the output stage, the collectors and emitters of IGBTs 11 and 12 are connected in series between the voltage terminal and the ground terminal. The input terminal of a load 14 such as a motor is connected to an output terminal 13 as a connection point between the emitter of the IGBT 11 and the collector of the IGBT 12.
High- and low-side driving circuits are connected to the IGBTs 11 and 12, respectively. A low-side driving circuit 10 connected to the gate of the IGBT 12 will be described here.
An ON/OFF input signal is input from an external control system (not shown) to an input terminal 21 of the driving circuit 10. The input ON/OFF input signal is supplied to a high-side buffer stage 32 and low-side buffer stage 34 through a gate output control circuit 31.
A gate output high-level switching element 33 which has a switching element SW1 and resistor R1 connected in series with each other and a gate output low-level switching element 35 which has a resistor R2 and switching element SW2 connected in series with each other are connected in series between the voltage terminal and the ground terminal.
The ON/OFF signal is supplied to the switching elements SW1 and SW2 through the buffer stages 32 and 34. One of the switching elements SW1 and SW2 is turned on, and the other is turned off. ON/OFF control is thus executed. While the switching element SW1 is ON, and the switching element SW2 is OFF, a gate output signal of high level is generated at the connection point between the resistors R1 and R2. While the switching element SW1 is OFF, and the switching element SW2 is ON, a gate output signal of low level is generated.
The gate output signal is output from an output terminal 22 and supplied to the gate of the IGBT 12. When the gate output signal is high level, the IGBT 12 is turned on. When the gate output signal is low level, the IGBT 12 is turned off. In this way, the low-side IGBT 12 is ON/OFF-controlled. The level of the output terminal 13 is determined by the ON/OFF states of the IGBTs 11 and 12 and supplied to the load 14.
When the resistors R1 and R2 are arranged between the switching elements SW1 and SW2, the gate output moderately changes in rising to high level or dropping to low level. Hence, noise generation can be prevented when the IGBT 12 is ON/OFF-controlled and, more especially, turned off.
However, a parasitic capacitance CGCL is present between the emitter and the gate of the IGBT 12, as shown in FIG. 5. Assume that the gate output signal is low level, and the IGBT 12 is in the OFF state. For example, when the high-side IGBT 11 is turned on, and the voltage of the output terminal 13 varies, a displacement current flows through the parasitic capacitance CGCL so that noise is generated at the gate of the IGBT 12.
If the gate potential increases due to the influence of the noise, the IGBT 12 which should be in the OFF state is erroneously turned on. If the IGBT 12 is erroneously turned on, a through current flows between the IGBTs 11 and 12 which are in the ON state. Hence, the current consumption increases.
To prevent such an operation error, a conventional gate driving circuit shown in FIG. 6 has a gate output shunt switching element 70 such that the output terminal 22 is forcibly connected to the ground terminal while the IGBT 12 should be turned off. Accordingly, even when noise is generated at the output terminal 13, any increase in gate output signal is suppressed, and the IGBT 12 is prevented from erroneously being turned on.
A switching element SW3 of the gate output shunt switching element 70 is ON/OFF-controlled by an output shunt control circuit 50.
The output shunt control circuit 50 causes a comparator 62 to monitor the gate output level of the output terminal 22. When the gate output level drops to a reference voltage Vref (e.g., 2 V), the comparator 62 outputs an ON signal. This output is held by a latch circuit 63, output from an output terminal 52 as a shunt control signal, and supplied to the switching element SW3 through a buffer stage 64.
However, even this conventional gate driving circuit has the following problems.
As the first problem, the number of elements that constitute the comparator 62 is large, resulting in an increase in circuit area.
As the second problem, the elements that constitute the comparator 62 have a characteristic variation. To increase the accuracy of comparison with a reference voltage 61, the element size needs to be set large. This leads to an increase in circuit area and current consumption.
As the third problem, when the comparator 62 is used, the reference voltage 61 is necessary. To supply the reference voltage 61, an external or internal reference voltage generation circuit must be added. This also leads to an increase in area of the entire device.
As the fourth problem, the comparator 62 compares one reference voltage Vref with the gate output level. To prevent noise generation, preferably, the switching element SW3 for gate output shunt is turned on when the level of the output terminal 22 gradually drops and sufficiently becomes as low as, e.g., 2 V and is then set at the ground voltage.
Conversely, after the gate output of the output terminal 22 is at the off level, and the switching element SW3 for gate output shunt is temporarily turned on, the switching element SW3 is preferably prevented from being turned on even when the gate output increases such that the switching element SW3 maintains the ON state even when the level of the output terminal 22 increases due to noise.
For this purpose, a latch circuit is added to hold the OFF state. This also increases the area.
Known prior arts that disclose conventional gate driving circuits are as follows.
Japanese Patent Laid-Open No. 2002-43914 Japanese Patent Laid-Open No. 2001-16082 Japanese Patent Laid-Open No. 2000-286687 As described above, the conventional gate driving circuit has no sufficient measures against the through current due to noise. In addition, the number of elements that constitute an output shunt control circuit serving as a measure is large, resulting in an increase in circuit area and current consumption.